Is there a way to convert between SchedMachineModel and Itineraries?

Is there a way to convert between SchedMachineModel and Itineraries?

I was trying to write a very simple VLIW packetizer (Hexagon was my starting point). It turns out that current DFAPacketizer is using itineraries, but my schedule is based on SchedMachineModel (I was recommended to use it since the itineraries are being phased out). I was wondering if there is an automated tool that would convert from SchedMcahineModel to Itinerary based mode? As far as I understand they both convey the same information so there should be a way to convert between them.

Anybody? Does anyone at all know how to do it?

From: "Rail Shafigulin via llvm-dev" <llvm-dev@lists.llvm.org>
To: "llvm-dev" <llvm-dev@lists.llvm.org>
Sent: Monday, November 9, 2015 10:09:07 AM
Subject: Re: [llvm-dev] Is there a way to convert between SchedMachineModel and Itineraries?

Anybody? Does anyone at all know how to do it?

There is no direct conversion. Although they are similar models, they are different. The strength of Itineraries lies in modeling pipelines with complex hazards (especially those that are not fully pipelined, or have other similar ordering constraints). SchedMachineModel can't do that. Unless you need to represent those kinds of constraints, SchedMachineModel is preferred. We'd like to move toward using SchedMachineModel for most things.

-Hal

Thanks for the reply Hal. I thought my thread was dead.

I was recommended to use SchedMachineModel for my VLIW, which is what I've
done (it took me a month to learn tblgen and write the scheduling model and
one more month do get my head around LLVM. My experience with compilers is
limited to a class I took in college a year ago). The scheduling part seems
to be working (at least this is what my limited testing shows). However
current DFAPacketizer is based on itineraries (DFAPacketizer.cpp, lines
66-73). I was hoping there is a way to convert between these two
representations so that I wouldn't have to rewrite the packetizer.
Unfortunately my experience with compilers is very limited and I still have
a lot to learn.

Right now I have two options. In both of the cases there are significant
drawbacks.
1. Rewrite the scheduling model using itineraries. Unfortunately there is
very little help available on this topic, I even asked on the IRC channel
and nobody seems to know how it is done, since everyone is moving towards
the SchedMachineModel.
2. Write a new packetizer which will use the SchedMachineModel, however, as
I said before, I have a very limited experience with compilers and this
looks like some major work. I'm not afraid of it, it is just there is not
much information and help available.

I would greatly appreciate any help on this

Rail

Not many people work with either the machine model or itineraries.

Be careful! I think the DFAPacketizer will only be effective on a very simple itinerary (which could easily have been expressed in the new machine model instead). I’ve heard stories of it “blowing up” on large itineraries. I have no direct experience with it.

This looks like an opportunity for you to learn something interesting. Generating a state machine from a set of constraints is fairly straightforward. The only difficultly lies in limiting the total number of states so you don’t end up with a giant table. If you were able to express those constraints in the machine model they must not be too complicated.

If your state machine is really just modeling the number of functional units that can be used by a given VLIW bundle, then you don’t need to generate a state machine at all. All you need are counters. MachineScheduler can do this for you. It already has some support for scheduling instruction groups for a simple in-order machine (without plugging in your own scheduler at all). Currently, this isn’t fully implemented—it isn’t modeling multiple functional units per cycle. But that would be very easy to fix and is something I could help with. It’s just that no one has asked for it.

Andy

Not many people work with either the machine model or itineraries.

Andrew's right; not too many people on the list work with the itineraries It was authored for the Hexagon backend and I believe the R600 uses it as well.

How complex are the bundling rules in your VLIW target? Is that documented somewhere? The complexity will determine whether I'd recommend using the DFA packetizer.

-Anshu

Anshu,

Thanks for the reply

How complex are the bundling rules in your VLIW target? Is that documented
somewhere? The complexity will determine whether I'd recommend using the
DFA packetizer.

Bundling rules are actually quite simple. I think the only restriction that
I have is not to bundle two branches together. As far as documentation
goes, this is a proprietary project and it is not in the public domain, at
least for now. The reason we wanted to use existing packetizer is because
we thought that there is no need to re-invent the wheel. Why not use what
is already there?

Also given that I'm new to all of this (including VLIW architecture), my
boss told me to develop simple code just for 2 slots and later we'll try to
expand it. So when I say that bundling rules are quite simple, what I mean
is that they are quite simple for 2 slots, however when we extend it to
more slots, the rules might get more complicated.

Thanks,
R

Although currently out of tree, the Movidius SHAVE compiler also makes extensive use of Itineraries. It has some fairly complex scheduling requirements that I have so far not figured out how to express with the SchedMachineModel approach. It too is a VLIW processor, with predication and no instruction interlocking, so computing the correct scheduling is not just important for performance it is critical for correct code generation.

Curiously enough, a few months ago I posed a similar question, but the other way around regarding how to rewrite our scheduler to avoid using the itineraries - this thread has sort of answered that question J

Thanks,

Martin O’Riordan - Movidius Ltd.

Bundling rules are actually quite simple. I think the only

restriction that I have is not to bundle two branches together.

If that's the only restriction you want to implement, then you don't need to specify slot information in the DFA. You can add the branch check to <your-target>VLIWPacketizer.cpp. Look at HexagonVLIWPacketizer.cpp for examples on how to add checks during packetizing.

> however when we extend it to more slots, the rules might get more complicated.

If the slot rules get complicated beyond the branch check, then you should consider using the DFA.

-Anshu

2. Write a new packetizer which will use the SchedMachineModel, however,

as I said before, I have a very limited experience with compilers and this
looks like some major work. I'm not afraid of it, it is just there is not
much information and help available.

This looks like an opportunity for you to learn something interesting.
Generating a state machine from a set of constraints is fairly
straightforward. The only difficultly lies in limiting the total number of
states so you don’t end up with a giant table. If you were able to express
those constraints in the machine model they must not be too complicated.

If your state machine is really just modeling the number of functional
units that can be used by a given VLIW bundle, then you don’t need to
generate a state machine at all. All you need are counters.
MachineScheduler can do this for you. It already has some support for
scheduling instruction groups for a simple in-order machine (without
plugging in your own scheduler at all). Currently, this isn’t fully
implemented—it isn’t modeling multiple functional units per cycle. But that
would be *very* easy to fix and is something I could help with. It’s just
that no one has asked for it.

Andy

I would love to work on the new packetizer, but (there is always a but
isn't it :slight_smile: ) we are so resource and schedule constrained that we can't
really devote any time to it. I'm very saddened by it. I think it is a
great project and I would love to be involved in it. Anyways, thanks for
all the help and advice. I really appreciate it.

R

It has some fairly complex scheduling requirements that I have so far not figured

out how to express with the
> SchedMachineModel approach. It too is a VLIW processor, with predication and no instruction interlocking,
> so computing the correct scheduling is not just important for performance it is critical for correct code generation.

That's interesting to know. The compiler is responsible for generating the correct schedule on Hexagon as well. I'd say Hexagon packets have moderately complex resource restrictions. And we're able to express those restrictions in the DFA.

-Anshu