Is there a way to create a hash of synthesizable Verilog?

I would like to create a hash of the synthesizable Verilog. Only if this hash changes, do I run a new P&R&S.

Let’s say I change some Chisel comments and move some lines in the .scala source code, then I don’t want a new P&R&S.

Even if I strip the comments, there’s still e.g. assert()s that can refer to .scala line numbers, so I need all non-synthesizable code scrubbed.

Can I use firtool to generate such synthesizeable Verilog only files and then create a hash?

To give a bit more meat on the bone: there is at least one tool that don’t guarantee the same result unless the files are identical, even including comments:


I think the short answer is no, for the same reasons as Is there a way to generate Verilog stripped of non-synthesis code?. If it would be useful to be able to cordon off non-synthesizable constructs, we can have a discussion about how to implement such a thing.