Hi everyone!
I have a question regarding the block merging done in Transforms/Utils/RegionUtils.cpp
When I have two basic blocks containing a store or a signal drive each, those blocks will be merged and the pointer/signal resp. will be passed via new block arguments. However, this makes further analyses and transformations more difficult than necessary and I think it’s an optimization in the wrong direction for our dialect.
Is it possible to turn block merging off in the case when new arguments have to be added (without changing the MLIR source code)? If not, is this a planned feature?
Here an example using LLHD (part of CIRCT):
llhd.proc @unwanted_merge_blocks2() -> (%arg0 : !llhd.sig<i1>, %arg1 : !llhd.sig<i1>) {
%0 = llhd.const #llhd.time<0s, 0d, 1e> : !llhd.time
%1 = llhd.const #llhd.time<0s, 1d, 0e> : !llhd.time
%2 = llhd.prb %arg0 : !llhd.sig<i1>
cond_br %2, ^bb1, ^bb2
^bb1: // pred: ^bb0
llhd.drv %arg1, %2 after %0 : !llhd.sig<i1>
llhd.halt
^bb2: // pred: ^bb0
llhd.drv %arg0, %2 after %1 : !llhd.sig<i1>
llhd.halt
}
is transformed to
llhd.proc @unwanted_merge_blocks2() -> (%arg0 : !llhd.sig<i1>, %arg1 : !llhd.sig<i1>) {
%0 = llhd.const #llhd.time<0s, 0d, 1e> : !llhd.time
%1 = llhd.const #llhd.time<0s, 1d, 0e> : !llhd.time
%2 = llhd.prb %arg0 : !llhd.sig<i1>
cond_br %2, ^bb1(%arg1, %0 : !llhd.sig<i1>, !llhd.time), ^bb1(%arg0, %1 : !llhd.sig<i1>, !llhd.time)
^bb1(%3: !llhd.sig<i1>, %4: !llhd.time): // 2 preds: ^bb0, ^bb0
llhd.drv %3, %2 after %4 : !llhd.sig<i1>
llhd.halt
}
(Note: I have disabled cond_br canonicalization to make the example more minimal)
Thanks,
Martin