ISel using an operand as both source and destination

I have some instructions that use a register as both an input and as the output. Is there a way to specify this constraint in the or will this have to be custom selected/lowered?


I see in the x86 the following for the INC instructions:

def INC8r : I<0xFE, MRM0r, (ops GR8 :$dst, GR8 :$src), "inc{b} $dst",
                [(set GR8:$dst, (add GR8:$src, 1))]>;

Which seem to have the same restriction that I'm trying to implement, but I don't understand how this ensures that $src and $dst are the same register.

The trick is that it's nested in this block:

let isTwoAddress = 1 in {

Marking an instruction 'two address' tells the codegen that the first two registers must be constrained to be the same physreg. There is a more general mechanism wih constraints you can also use.


Yes, please use operand constraint instead (see class Instruction, field Constraints in isTwoAddress is left in only because I am too lazy to convert all the existing patterns to operand constraint.

In this example, the constraint would look like "$src = $dst". ARM has some examples if you are interested.