IselDagtoDag Matching when an instruction updates more than one register [RISCV backend]

Consider a custom instruction available in the processor, say
fupdt rd, rs1, rs2
where the semantics is

rd = rs1 * rs2
rs1 = rs1 + rs2

In this case, as mentioned above, both registers rd and rs1 are updated.

I have two questions

  1. How is the custom instruction specified in a table gen file while specifying the DAG (in I get an error if I specify $rs1 also in the outs list.
class CustInst<bits<7> funct7, bits<3> funct3, string opcodestr>
    : RVInstR<funct7, funct3, OPC_FUPDT, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
              opcodestr, "$rd, $rs1, $rs2"> ;
  1. How to select this custom instruction via either RISCVISelDAGToDAG or tablegen pattern?
    I understand how DAG matching works in general, but I am unable to find a concrete example, where two instructions can be replaced by a single instruction with 3 inputs and 2 outputs.

Two inputs, two outputs, and tie the second output to the first input via Constraints.

Thanks for the quick response. Is it possible to share a link to a commit or a code snippet that explains this concept?