Consider a custom instruction available in the processor, say
fupdt rd, rs1, rs2
where the semantics is
rd = rs1 * rs2 rs1 = rs1 + rs2
In this case, as mentioned above, both registers rd and rs1 are updated.
I have two questions
- How is the custom instruction specified in a table gen file while specifying the DAG (in
RISCVInstrInfo.td)? I get an error if I specify $rs1 also in the outs list.
class CustInst<bits<7> funct7, bits<3> funct3, string opcodestr> : RVInstR<funct7, funct3, OPC_FUPDT, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2), opcodestr, "$rd, $rs1, $rs2"> ;
- How to select this custom instruction via either RISCVISelDAGToDAG or tablegen pattern?
I understand how DAG matching works in general, but I am unable to find a concrete example, where two instructions can be replaced by a single instruction with 3 inputs and 2 outputs.