itineraries for x86 and optimization in the target

Hello,

Is there code in place for lowering the bitcode SSA into an optimized sequence for the itineraries? I have been curious whether or not such descriptions exist for the x86 family or whether there are techniques to make a clear determination of this information.

Regards,

Carter.

This thread might partially answer your question:

http://thread.gmane.org/gmane.comp.compilers.llvm.devel/43347

-Andy

Thanks Andy.