L1, L2 Cache line sizes in TargetData?


Is there any way for a pass to determine the L1 or L2 cacheline size
of the target before the IR is lowered to machine instructions?


LLVM doesn't currently have any target-specific memory hierarchy
information, so the way to do it would be to design an interface for
this information, perhaps named something like TargetMemoryInfo,
and initially populate it with things that you need.