Layout of FXSAVE struct for x86 Architectures in LLDB

Hi all

I was looking into the file “source/Plugins/Process/Utility/RegisterContext_x86.h” and I noticed one thing in FXSAVE structure. The ‘ftag’ is defined as a 16 bit field.

However, on referring to Architecture Software Developer Manual for x86 architectures, one can see that the memory layout of the contents of FXSAVE area has only 8 bits for ‘ftag’ register and rest of the 8 bits are reserved. Is there any specific reason of keeping ‘ftag’ field to be 16 bits in FXSAVE structure in LLDB for x86 Architectures?

  • Abhishek

I’m using this doc:

http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-manual-325462.pdf

In table 10-2, and again in 13-1, it does appear to call out the most significant byte as reserved (byte 5). As do the instruction details.

Looking at the in-memory layout of the FPU tag word in “8.1.7 x87 FPU Tag Word”, it is clear all 16 bits are used in the runtime image, and the 8 bits of defined ftag state in the FXSAVE area are encoded/decoded as per byte 4’s description in section 10.5.1.

Seems fine to call it what it is - want to put up a patch? Just make sure you run all the tests as well.

-Todd