I met troubles with jitting x86 codes when using Intrinsic::x86_sse_ldmxcsr.
The target code must execute some SSE2 instruction with DAZ/FTZ modes enabled and others with DAZ/FTZ disabled.
I’m trying to get this by emitting LDMXCSR instructions with proper flag words.
It appeared however that execution engine sometimes reorders these instructions with computational ones (say with Intrinsic::x86_sse2_min_pd as we have in the scenario).
As a result, wrong floating point values are produced.
The issue disappears when using llvm::CodeGenOpt::None instead of Default, but of course this is too big hammer for using as a workaround.
Is it a bug, or am I missing some smart settings to prohibit reordering?