I just switched to the 2.5 release branch and noticed that llc runs into the following assert in ScheduleDAGList::ScheduleNodeTopDown() using our custom backend:
"The list-td scheduler doesn't yet support physreg dependencies!");
It turns out that the register dependency concerns the condition code register which is modeled as an implicitly defined register in the backend (the same happens for e.g. for X86 when explicitly giving the -pre-RA-sched=list-td option to llc).
My assumption is that the assert should exclude non-allocatable, implicitly defined registers, which is checked in the attatched patch1.
This works fine for me, however on X86 the EFLAGS register is not marked non-allocatable (patch2).
Is this intentional? Our backend handles condition codes pretty much like X86 and I remember I didn't get it to work without defining the allocation_order_end() function in RegisterInfo.td
Anyway, I have no idea if this solution is ok for the general case, maybe the implicit defs information should rather be put into the SDeps when they are created?
patch2_X86eflagsAllocatable.patch (649 Bytes)
patch1_physregAlloc.patch (1.6 KB)