live information

Hi,

I’m working on live intervals and I’m curious about how LLVM typically would represent live info. Take the following case (after SimpleRegisterCoalescer):

BB#3: derived from LLVM BB %bb.nph
Live Ins: %a0_h
Predecessors according to CFG: BB#2
%reg16500 = COPY %reg16499
Successors according to CFG: BB#4

BB#4: derived from LLVM BB %for.body21
Live Ins: %a0_h
Predecessors according to CFG: BB#3 BB#4
%reg16500 = add_twoAddr %reg16500, 1

cmp_branch <BB#4>, %reg16500, %a0_h
Successors according to CFG: BB#4 BB#5

BB#4 is a loop.

%reg16500 is first defined by a COPY, then updated at each iteration and used at the end as well of BB#4.

Live ins(BB#4) should include %reg16500 (Simple register coalescer did not care for this)
LiveRanges should be from the def in BB#3 to end of BB#3, from start of BB#4 to the add MI, from the add MI to the compare&branch MI.

Am I correct?

I am trying to recompute live-info after the coalescer, so I also wonder if any or both of the add and cmp_branch MI’s should have kill-flags for %reg16500?

Thanks,

Jonas

I’m working on live intervals and I’m curious about how LLVM typically would represent live info. Take the following case (after SimpleRegisterCoalescer):

BB#3: derived from LLVM BB %bb.nph
Live Ins: %a0_h
Predecessors according to CFG: BB#2
%reg16500 = COPY %reg16499
Successors according to CFG: BB#4

BB#4: derived from LLVM BB %for.body21
Live Ins: %a0_h
Predecessors according to CFG: BB#3 BB#4
%reg16500 = add_twoAddr %reg16500, 1

cmp_branch <BB#4>, %reg16500, %a0_h
Successors according to CFG: BB#4 BB#5

BB#4 is a loop.

%reg16500 is first defined by a COPY, then updated at each iteration and used at the end as well of BB#4.

Live ins(BB#4) should include %reg16500 (Simple register coalescer did not care for this)
LiveRanges should be from the def in BB#3 to end of BB#3, from start of BB#4 to the add MI, from the add MI to the compare&branch MI.

Am I correct?

The live-in lists on basic blocks are only used for physical registers. The are filled in after register allocation is complete by RegAllocBase::addMBBLiveIns.

I am trying to recompute live-info after the coalescer, so I also wonder if any or both of the add and cmp_branch MI’s should have kill-flags for %reg16500?

Kill flags are very difficult to keep updated when coalescing and allocating registers, so they are simply cleared by the coalescer and reinserted afterwards by LiveIntervalAnalysis::addKillFlags.

Thinking about it, it may make sense to also use kill flags for physical registers only.

/jakob