llc support for ARM predication ?

Hi all,

I was wondering if 'llc' is able to generate 'it' instruction for ARM Cortex-A9 target ?

Thanks for your answers
Seb

Hi Seb,

Sure - llc can generate 'IT' instructions, but those are Thumb instructions so will only be generated with the target triple "thumbv7-..." instead of armv7.

Cheers,

James

Hi James,

Thanks for the answer, can you elaborate on difference between thumb, thumb2, ARM, thumbv7.
I'm a bit lost right now. When specifying thumbv7 llc will generate thumb only code, not thumb2 ?

Best Regards
Seb

Hi Seb,

The ARM instruction set is a fixed-width 32-bit instruction set that has
been around since the early days of ARM.

Modern (armv4t onwards) cores mostly have another instruction set that
can be used in tandem, the "thumb" instruction set. This is a variable
width (16 or 32 bit) instruction set that provides a subset of the ARM
instruction set and was intended to provide the amount of functionality
that compilers required and no more, to reduce codesize in compiled images.

What was "thumb" became referred to as "thumb1" after "thumb2" was
released (armv6t2), which added features such as condition execution
(the IT, "if-then-else" instruction).

The ARM architecture is numbered sequentially by evolution, so Thumb is
available in v4t (meaning "v4 with Thumb extension") and Thumb-2 is
available in v6t2.

v7 includes Thumb-2 by default (for A-class cores such as Cortex-A8). So
when specifying "thumbv7" as the architecture to LLVM, LLVM will
generate Thumb-2 instructions and use IT instructions for conditional
execution.

Hope this helps,

James

Hi James,

Thanks for the answer, for Cortex-A9 would you recommend to generate thumb2 code or ARM code ? What would be the best performance wise ?

Best Regards
Seb

Hi Seb,

That really depends on your workload. You should benchmark with both and choose the best.

Cheers,

James