LLVM and VHDL simulation

Hi,

I am wondering if someone knows about a VHDL simulator (maybe still in early developpement) that use LLVM in its compilation process.
To summarize, VHDL is a hardware description language, which means that VHDL is like any other programming language except that the output of its synthesis is not a list of assembly instructions but a description of a circuit with logical gates. This description is then translated to hardware (which is often done in practice by programming a FPGA).
In consequence, after being synthetised on hardware, not all the VHDL instructions are meant to be executed serially like it is for assembly instructions but they could also be concurrent.
VHDL code could also be simulated by a simulator in which case the concurrent instructions are of course executed serially because the VHDL code is compiled in this case to assembly instructions.
I have no experience with LLVM, but it seems to me that if a VHDL simulator use LLVM for its middleend and backend, it would be hard (if not impossible) to exploit the concurrency of the concerned instructions to do further optimizations.
I find that the author of GHDL (a free VHDL compiler and simulator that is probably the most mature among the free ones) said once to be interested of modifying GHDL to compile to LLVM (see http://www.ruby-forum.com/topic/155103), but now it doesn't seems that anything concrete was made for this project in this area.

Greetings,
Jonas

I don’t have a solution for you, but when you found one or start the project on your own, let me know.

I first used LLVM and CLang for iOS development, and was especially
impressed with how the static analyzer improved my Objective-C and
Cocoa Touch code.

But what got me interested in joining the CLang and LLVM development
was that Mentor Graphics was advertising for an LLVM developer to
produce VHDL tools for Mentor to sell as a product. The job ad on
Mentor's website specifically said the position could be full-time
telecommute.

Unfortunately for me, they want someone who is an already established
LLVM contributor, and I have yet to build my first source drop!

Thanks for your answers.

In one year, I am going to have something like a semester project.
The idea I have for this project would be to create (for simulation only) a VHDL front-end to LLVM, compile some VHDL code with the newly created compilator and also with a commercial compilator and simulator and compare the performance of both simulations. I won't have the time to do a full VHDL support, but if I implement at least entities/architectures, concurrent statements, processes, integer and/or real and boolean types, that should be enough to do the comparison. Maybe after the project, I will continue to work on the VHDL front-end. The main point of this project will be to see what LLVM could bring in term of performances and ease of developpement.
This project has still to be accepted, so I am not 100% sure that I will do this project. I also found a tutorial (http://llvm.org/docs/tutorial/) that can help me to familiarize with LLVM before I will do this project (if I will).

Greetings
Jonas

Hi,

I am wondering if someone knows about a VHDL simulator (maybe still in early developpement) that use LLVM in its compilation process.
To summarize, VHDL is a hardware description language, which means that VHDL is like any other programming language except that the output of its synthesis is not a list of assembly instructions but a description of a circuit with logical gates. This description is then translated to hardware (which is often done in practice by programming a FPGA).
In consequence, after being synthetised on hardware, not all the VHDL instructions are meant to be executed serially like it is for assembly instructions but they could also be concurrent.

Does this 'concurrency' mean that we need to figure out
data-independent instructions in VHDL? Although LLVM-IR is written
serially, its SSA form explicitly tells us the data dependency between
temporaries. Then the question is how to map VHDL data types and
program constructors to LLVM, I think this is not trivial.

I just googled a System C-LLVM tool
  https://forge.imag.fr/plugins/mediawiki/wiki/pinavm/index.php/Main_Page
which may help?

I have posted the following message at the wrong place, sorry.

Does this 'concurrency' mean that we need to figure out
data-independent instructions in VHDL? Although LLVM-IR is written
serially, its SSA form explicitly tells us the data dependency between
temporaries. Then the question is how to map VHDL data types and
program constructors to LLVM, I think this is not trivial.

I just googled a System C-LLVM tool
  https://forge.imag.fr/plugins/mediawiki/wiki/pinavm/index.php/Main_Page
which may help?

Thanks for the link. I will look at it.

Suppose we have the following VHDL entity and architecture :

entity Test is
   port (A, B, C, D : in Bit;
         X, Y, Z : out Bit);
end Test;

architecture Test_RTL of Test is
begin

   X <= A And B;
   Y <= C And D;
   Z <= X Or Y;

end Test_RTL;

The previous block will be synthetized on hardware as a circuit with "AND" and
"OR" gates and without clock because there is only combinatorial logic. The
instructions that calculate X, Y and Z are concurrent so that it is allowed to
put them in any order, although the value of Z depends of the value of X and Y
(to have sequential instructions, a clock must be used).
It is for example allowed to change the order like this :

   Z <= X Or Y;
   X <= A And B;
   Y <= C And D;

because X, Y, and Z are not meant to be calculated sequentially on hardware,
but simultaneously (if we neglect the gate delays) after the change of any of
the inputs. When looking at the equivalent circuit, it is easy to see that no
matter is the order of statements, the synthetized circuit will always be the
same.

To simulate this entity, we will of course execute the instructions sequentially
and Z has to be calculated after X and Y. The order of calculation of X and Y
doesn't matter.

The only difficulty I see with this concurrency is to find a algorithm to
determine the sequence of the instructions to be executed before writing them
to LLVM-IR.

I hope that I answered your question.
Greetings,
Jonas

Baggett Jonas <Jonas.Baggett <at> hefr.ch> writes:

Hi,

I am wondering if someone knows about a VHDL simulator (maybe still in early

developpement) that use LLVM in

its compilation process.

http://github.com/nickg/nvc

NVC is a GPLv3 VHDL compiler and simulator

See these posts for more information:
  http://www.doof.me.uk/2011/11/05/writing-a-vhdl-compiler/
  http://www.doof.me.uk/2012/04/15/vhdl-compiler-improvements/

To build from a Git clone:
  ./autogen.sh
  mkdir build && cd build
  ../configure
  make
  make install

To use a specific version of LLVM add
  --with-llvm=/path/to/llvm-config
to the configure command. LLVM 3.0 or later is required.

To run the regression tests:
  make check
Note you may need to install additional Ruby libraries:
  gem install colorize getopt

To recompile the standard libraries:
  make -C lib clean
  make bootstrap
Note this happens automatically when installing.