I have a question regarding LLVM backend. I appreciate a lot if anyone can provide some hints.
My work here is to avoid base+index address mode for X86 target, to allow base-register only or index-register only address mode. For example,
“mov (%rsi), %rbx” is allowed, but “mov (%rsi, %rax), %rbx” is not allowed.
I understand LLVM backend is a complex system. Can any one help point out which subsystem I should look into to solve my question?
For experimental purposes, you should be able to just go into lib/Target/X86 and remove the patterns in .td files (or maybe some .cpp … I’m not familiar with the X86 mechanisms) that map to base+index addressing modes.
Then the compiler will automatically use some extra temporary register to calculate intermediate addresses.
Thanks for you reply.
I check the *.td files under the lib/Target/X86 folder, but have not got interesting findings. It requires some knowledge of LLVM backend to fully understand the *.td files. I will get some background and keep searching.
Of course I appreciate if anyone with such experience can point the concrete locations.
I think the code your looking for starts at X86DAGtoDAGISel::selectAddr in X86ISelDAGtoDAG.cpp.
For some definition of “starts”
Looks like X86DAGToDAGISel::MatchAddressRecursively is the actual thing to hack up.
Yes, starting from X86DAGtoDAGISel::selectAddr, the code calls X86DAGtoDAGISel::selectAddr to resolve the address mode.
But it seems there is no centralized control on the address mode. Have to patch the code in several places.
Maybe modify X86TargetLowering::isLegalAddressingMode to make base+index illegal?
Found some related code in Native Client implementation.
It mainly hacks the X86DAGToDAGISel::matchAddressBase to assign the SDNode to the index register, instead of using base register first. Other hacks try to avoid assign SDNode to base register.
I’m still checking Native Client’s implementation. Will check the X86TargetLowering::isLegalAddressingMode.