LLVM backend, unique operands in instruction


I’m trying to add an instruction (in the InstrInfo.td file).
The instruction does not support using the same register in the input and output.

I’ve tried to use Constraint, but it appears that it’s only support same register (“$rs = $rd”).

Is there a way to implement that?

Mark the output register as “early clobber”, i.e. Constraints = "@earlyclobber $rd".

Thank you so much! :smiley:

I tried it and it worked.
I do wonder though, what other effects it might have?

I’ve looked this up and it looks like it’s saying that $rd needs to be calculated before $rs is read?
If I’m wrong I’d like to know what it actually does, either way I would like to know if there’s a cost to this way.

That’s pretty much what it means, and this is the exact use case for it. There is no additional cost implied here.

Got it.
Thanks a lot! :slight_smile: