LLVM code target dependent generator question

I am new to LLVM and I am not sure whether I am writing to the right distribution list or not. Please let me know if this is not the right distribution list.

- I am having hard time lowering ADD instructions for different purposes. Basically, I want to have different machine instruction for pointer addition vs scalar addition. I am having hard time mapping LLVM add to my machine add instruction based on the oprand types.

Here is the sample code:

void myFunction( int* src, int* dst, int i )
  dst[i] = src[i];

  i = i + 4;


I want to get this translate to my machine code as following:
shl R1028, R1026, 2
add_pointer R1029, R1024, R1028 // incrementing the src pointer
load R1030, R1029
add_pointer R1031, R1025,R1028 // calculating the dst address
store R1030, R1031
mov R1031, 4
add R1032, R1026, R1031 //scalar addition

Currently my ADD instruction is defined in the InstrInfo.td file as following:

def I32RC : RegisterClass<"MyMachine", [i32], 32, [DefReg]>;
def P32RC : RegisterClass<"MyMachine", [iPTR], 32, [DefReg]>; -> I get error from tablegen if I use iPTR

def MyAdd : MyInst
(outs I32RC:$dst),
(ins I32RC:$src1, I32RC:$src2),
“add $dst, $src1, $src2",
[(set rc:$dst, (add I32RC:$src1, I32RC:$src2))]

def MyPointerAdd : MyInst
(outs P32RC:$dst),
(ins P32RC:$src1, P32RC:$src2),
“pointer_add $dst, $src1, $src2",
[(set rc:$dst, (add P32RC:$src1, P32RC:$src2))]

Does this look right? If not please advice me on how to get my desired result.
Can I get the desired result by changing my targetInstrInfo.td file only? Or do I have to manually implement the lower add instructions for my target? And when I check the type of add operand when LLVM->LLC generates the code for LLVM IR, the type of the pointer operand is i32. So, I am not sure how to distinguish between pointer types vs scalar types

Your help is highly appreciated and thank you in advance for your help