OK from what I understand, the DAG.getSExtOrTrunc(SetCC, DL, SelectVT)
is unecessary and the SelectVT is nto the right type (as it is called with
incorrect parameter).
Here is a patch so it won't generate a loop. I ran make check and it
doesn't look like anything is broken.
No, it is necessary and is the fundamental change in that commit. SelectVT
is not necessarily the same as VT, so it needs to be converted. This patch
breaks the testcases I have that this fixed. If it helps, this is the
testcase I was fixing.
define i32 @test_sext_icmp_i64(i64 %arg) {
%x = icmp eq i64 %arg, 0
%y = sext i1 %x to i32
ret i32 %y
}
So this is not possible ?
(select (i64 setcc ...), (i32 -1), (i32 0))
The setcc type is i64 for the i64 icmp, so it then needs to be truncated
to 32-bits in this situation
I understand this? Why does the setcc needs to be truncated ? It doesn't
look like it usually is.
I have a test case which is exactly the other way around :
define i32 @test_sext_icmp_i32(i32 %arg) {
%x = icmp eq i32 %arg, 0
%y = sext i1 %x to i64
ret i64 %y
}
The DAG.getSExtOrTrunc(SetCC, DL, SelectVT) is returning the node
DAGCombiner is working on, which create a loop after the substitution. If I
have X = (i64 (sext (i32 (setcc A B)))) to be "combined" as (select X, -1,
0) and then, after substitution occurs, the select become its own
condition, creating a loop in the DAG.