[llvm dev] do we have allocator hook to use maximum different registers?

Hi,

Default register allocator tries to reuse the same registers over and
over again even if register file have a plenty of registers to use.
This creates parasite false dependencies and makes scheduling less
effective.

How to instruct allocator (may be override some virtual function in
mine backend?) that it is profitable to use maximum number of
available registers with minimal dependencies? In GCC this option is
known as -frename-registers.

Hi Konstantin,

Hi,

Default register allocator tries to reuse the same registers over and
over again even if register file have a plenty of registers to use.
This creates parasite false dependencies and makes scheduling less
effective.

How to instruct allocator (may be override some virtual function in
mine backend?) that it is profitable to use maximum number of
available registers with minimal dependencies?

That is not possible and in the current scheme that would be hard to add. Indeed, the greedy reg alloc assigns live-ranges in an order based on some priority cost model. Thus, we do not know how close, in the scheduling order, two live-ranges are when we assign them in a row.

Cheers,
-Quentin

On an OOO register renaming should make this issue mute. On an IOP experimenting with round robin vs stack assignment could be interesting. For caller save registers round robin would be ok. For callee saved registers the potential extra prolog/epilog spills/fills need to be taken into account. And this is probably just the start of the tuning fun.

-Gerolf

IOP is pretty common with mobile.. (maybe that's changed?)

Apple A9, Qualcomm Kryo == OoO
latest kirin == mixed a53/a72 arm cores

For me IOP optimizations around regalloc are very interesting.. please
feel free to share any verbose details. It's something we may
potentially be able to help with as well as upstream.

Hello Konstantin,
   we approach this issue by using pre-RA scheduling and it works fine,
although for very large basic blocks, the effect is not so good, because it leads to more spilling
comparted to the case when a pre-RA schedule is not used.

I also remember that there is some interface for schedulers
to do the register renaming, but as far as I know, we haven't used it yet.

Best regards
   Adam

Hi,

Adam,

Can you please be more verbose on how pre-RA scheduling may help in
this case? How should I schedule instructions with virtual registers
in order to instruct allocator to use maximum physical ones?