LLVM ERROR: Cannot select: intrinsic while adding a new RISCV intrinsic

Hi,

I’m trying to add a custom intrinsic to the RISCV target and I followed the instructions here, I added the intrinsic definition to IntrinsicsRISCV.td and the implementation to RISCVISelLowering.cpp under SDValue RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG). The code is attached below. When I try to use the intrinsic to compile a llvm code I get an error message saying LLVM ERROR: Cannot select: intrinsic %llvm.riscv.padd

I would REALLY appreciate any help or pointer regarding this!

Thank you!
-Farzana

IntrinsicsRISCV.td:

let TargetPrefix = "riscv" in {
  def int_riscv_padd : DefaultAttrsIntrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty], [IntrWriteMem, ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>]>;
}

RISCVISelLowering.cpp:

case Intrinsic::riscv_padd: {
    SDValue Op1 = Op.getOperand(1);
    SDValue Op2 = Op.getOperand(2);
    SDLoc DL(Op);
    DAG.getNode(ISD::ADD, DL, MVT::i64, Op1, Op2);
    return Op1;
 }

Test .ll

target datalayout = "e-m:e-p:64:64-i64:64-n64-S128"
target triple = "riscv64"

; Define the main function
define void @main() {
  ; Call the intrinsic function
  %res = call i64 @llvm.riscv.padd(i64 6, i64 1)
  ret void
}

; Declare the intrinsic function signature
declare i64 @llvm.riscv.padd(i64, i64)

Stack Trace

LLVM ERROR: Cannot select: intrinsic %llvm.riscv.padd
PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace.
Stack dump:
0.	Program arguments: ./build/bin/llc -march=riscv64 -debug=1 ./test.ll -o outp.s
1.	Running pass 'Function Pass Manager' on module './test.ll'.
2.	Running pass 'RISC-V DAG->DAG Pattern Instruction Selection' on function '@main'
 #0 0x00005650c784c8e2 llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) /home/farzana/Research/riscv_die/llvm-project/llvm/lib/Support/Unix/Signals.inc:723:22
 #1 0x00005650c784ccf3 PrintStackTraceSignalHandler(void*) /home/farzana/Research/riscv_die/llvm-project/llvm/lib/Support/Unix/Signals.inc:798:1
 #2 0x00005650c784a276 llvm::sys::RunSignalHandlers() /home/farzana/Research/riscv_die/llvm-project/llvm/lib/Support/Signals.cpp:105:20
 #3 0x00005650c784c19c SignalHandler(int) /home/farzana/Research/riscv_die/llvm-project/llvm/lib/Support/Unix/Signals.inc:413:1
 #4 0x00007f6c60ea5420 __restore_rt (/lib/x86_64-linux-gnu/libpthread.so.0+0x14420)
 #5 0x00007f6c6094200b raise /build/glibc-BHL3KM/glibc-2.31/signal/../sysdeps/unix/sysv/linux/raise.c:51:1
 #6 0x00007f6c60921859 abort /build/glibc-BHL3KM/glibc-2.31/stdlib/abort.c:81:7
 #7 0x00005650c7780f82 llvm::report_fatal_error(llvm::Twine const&, bool) /home/farzana/Research/riscv_die/llvm-project/llvm/lib/Support/ErrorHandling.cpp:125:9
 #8 0x00005650c75dac6f /home/farzana/Research/riscv_die/llvm-project/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:3914:21
 #9 0x00005650c75da3a3 llvm::SelectionDAGISel::SelectCodeCommon(llvm::SDNode*, unsigned char const*, unsigned int) /home/farzana/Research/riscv_die/llvm-project/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:3817:9
#10 0x00005650c5d90bdc llvm::RISCVDAGToDAGISel::SelectCode(llvm::SDNode*) /home/farzana/Research/riscv_die/llvm-project/build/lib/Target/RISCV/RISCVGenDAGISel.inc:1125765:0
#11 0x00005650c5d82e5d llvm::RISCVDAGToDAGISel::Select(llvm::SDNode*) /home/farzana/Research/riscv_die/llvm-project/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp:2162:0
#12 0x00005650c75cb01d llvm::SelectionDAGISel::DoInstructionSelection() /home/farzana/Research/riscv_die/llvm-project/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1118:32
#13 0x00005650c75ca287 llvm::SelectionDAGISel::CodeGenAndEmitDAG() /home/farzana/Research/riscv_die/llvm-project/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:948:61
#14 0x00005650c75c891d llvm::SelectionDAGISel::SelectBasicBlock(llvm::ilist_iterator<llvm::ilist_detail::node_options<llvm::Instruction, true, false, void>, false, true>, llvm::ilist_iterator<llvm::ilist_detail::node_options<llvm::Instruction, true, false, void>, false, true>, bool&) /home/farzana/Research/riscv_die/llvm-project/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:702:1
#15 0x00005650c75ce21d llvm::SelectionDAGISel::SelectAllBasicBlocks(llvm::Function const&) /home/farzana/Research/riscv_die/llvm-project/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1707:33
#16 0x00005650c75c73f1 llvm::SelectionDAGISel::runOnMachineFunction(llvm::MachineFunction&) /home/farzana/Research/riscv_die/llvm-project/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:483:7
#17 0x00005650c5d908aa llvm::RISCVDAGToDAGISel::runOnMachineFunction(llvm::MachineFunction&) /home/farzana/Research/riscv_die/llvm-project/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h:39:3
#18 0x00005650c66a3d3a llvm::MachineFunctionPass::runOnFunction(llvm::Function&) /home/farzana/Research/riscv_die/llvm-project/llvm/lib/CodeGen/MachineFunctionPass.cpp:91:33
#19 0x00005650c6e8553d llvm::FPPassManager::runOnFunction(llvm::Function&) /home/farzana/Research/riscv_die/llvm-project/llvm/lib/IR/LegacyPassManager.cpp:1435:20
#20 0x00005650c6e8580b llvm::FPPassManager::runOnModule(llvm::Module&) /home/farzana/Research/riscv_die/llvm-project/llvm/lib/IR/LegacyPassManager.cpp:1481:13
#21 0x00005650c6e85c6a (anonymous namespace)::MPPassManager::runOnModule(llvm::Module&) /home/farzana/Research/riscv_die/llvm-project/llvm/lib/IR/LegacyPassManager.cpp:1550:20
#22 0x00005650c6e80b02 llvm::legacy::PassManagerImpl::run(llvm::Module&) /home/farzana/Research/riscv_die/llvm-project/llvm/lib/IR/LegacyPassManager.cpp:535:13
#23 0x00005650c6e86507 llvm::legacy::PassManager::run(llvm::Module&) /home/farzana/Research/riscv_die/llvm-project/llvm/lib/IR/LegacyPassManager.cpp:1678:1
#24 0x00005650c5c546f5 compileModule(char**, llvm::LLVMContext&) /home/farzana/Research/riscv_die/llvm-project/llvm/tools/llc/llc.cpp:754:66
#25 0x00005650c5c520b9 main /home/farzana/Research/riscv_die/llvm-project/llvm/tools/llc/llc.cpp:416:35
#26 0x00007f6c60923083 __libc_start_main /build/glibc-BHL3KM/glibc-2.31/csu/../csu/libc-start.c:342:3
#27 0x00005650c5c50dee _start (./build/bin/llc+0x12a4dee)
Aborted (core dumped)

Does it actually write to memory? An intrinsic without side effects and intrinsic that writes to memory have different ISD opcodes, take/return different values (chain vs no chain).

Thank you! Replacing IntrWriteMem with IntrNoMem solved the issue!