llvm installation

hello sir,
i am using llvm compiler for my project.i an doing llvm installation.i followed all the steps in the llvm website but after running this command

…/llvm/configure --enable-targets=host-only it executed but it didnt create any make file in build directory ,only config.log file is appeared after running this command.

after running the later command it is showing like this
manoj@ubuntu:~/Desktop/LLVM/
build$ make -j 4
make: *** No targets specified and no makefile found. Stop

please help me to finish installation. i am running installation in ubuntu os.

here is the config.log file …

config.log (66 KB)

configure:12131: $? = 0
configure:12145: result: yes
configure:12157: checking tool compatibility
configure:12180: error: g++|clang++|icc required but not found

configure can’t find a c++ compiler. On Ubuntu, please install g++ (sudo apt-get install g++).

This error should have been written to your console when you ran configure.

Hi Justin and all,

you've mentioned that you used an easy "trick" for defining an infinite register file in the backend.

Does this involve defining a single dummy register, and then adding this dummy reg to each register class? Is anything more needed? I refer to the RegisterInfo.td file, as e.g: llvm-3.0.src/lib/Target/PTX/PTXRegisterInfo.td

I'm (just starting) implementing an LLVM target that bares some similarities to PTX. One of these is the notion of infinite registers, since my target too is a kind of virtual/universal machine.

My target will not emit object files, so there i would prefer not to define a very larget register file and mess with formats. A bit-level format will at some point be defined but i don't want to fix it from now.

So your approach seems highly relevant.

Best regards
Nikolaos Kavvadias

Quoting Justin Holewinski <justin.holewinski@gmail.com>:

Hi Justin and all,

you've mentioned that you used an easy "trick" for defining an infinite
register file in the backend.

The original PTX back-end just didn't perform register allocation. All
registers emitted in the assembly were virtual registers, mapped to a
consecutive range. E.g., %vreg7, %vreg13, and %vreg72 might be emitted as
%r0, %r1, %r2. Just before machine code emission, we scanned the function
to determine this range. Unfortunately, during the switch to the NVPTX
back-end, some changes were made in LLVM that prevented this from working
in some cases. Basically, some post-regalloc passes were requiring
physical registers and choked when they saw virtual registers. Because of
this, the newer NVPTX back-end uses a large physical register file and
performs register allocation. It's not ideal, but I haven't had the time
to identify and fix every case where virtual registers won't work yet.

Does this involve defining a single dummy register, and then adding this
dummy reg to each register class? Is anything more needed? I refer to the
RegisterInfo.td file, as e.g: llvm-3.0.src/lib/Target/PTX/**
PTXRegisterInfo.td

You can define one dummy register, or one for each register class. You
only need to define the register classes that you support, and the way
tablegen generates code leads to compiler warnings about empty arrays if
you do not add at least one register to each register class.

I'm (just starting) implementing an LLVM target that bares some
similarities to PTX. One of these is the notion of infinite registers,
since my target too is a kind of virtual/universal machine.

It's a bit of an uphill battle since there are places in LLVM that make
assumptions about targeting a "real" architecture, to varying degrees. One
thing to keep in mind is that the PTX back-end from 3.1 may be a better
example to use than the NVPTX back-end in 3.2 and TOT. The original PTX
back-end supported less (and is therefore a bit simpler), and it also
doesn't suffer from as much backwards-compatibility cruft. NVPTX has
evolved over many LLVM revisions, and sometimes uses old techniques. I'm
working on getting it up to date.

Hi Justin,

The original PTX back-end just didn't perform register allocation. All
registers emitted in the assembly were virtual registers, mapped to a
consecutive range. E.g., %vreg7, %vreg13, and %vreg72 might be emitted as
%r0, %r1, %r2.

OK, I see.

I'm (just starting) implementing an LLVM target that bares some
similarities to PTX. One of these is the notion of infinite registers,
since my target too is a kind of virtual/universal machine.

It's a bit of an uphill battle since there are places in LLVM that make
assumptions about targeting a "real" architecture, to varying degrees. One
thing to keep in mind is that the PTX back-end from 3.1 may be a better
example to use than the NVPTX back-end in 3.2 and TOT. The original PTX
back-end supported less (and is therefore a bit simpler), and it also
doesn't suffer from as much backwards-compatibility cruft. NVPTX has
evolved over many LLVM revisions, and sometimes uses old techniques. I'm
working on getting it up to date.

Are you going to re-introduce the PTX backend in LLVM 3.3? I will certainly check PTX in LLVM 3.1 in order to draw some comparisons.

Best regards,
Nikolaos Kavvadias