Llvm-mca library.

Hi All,

I would like to use llvm-mca to estimate the IPC of a given code region. I am interested in the library version (https://reviews.llvm.org/D50929?id=162210) but I have troubles understanding how to use it. Could you please point me to some documentations or (better) some code examples if any?

Reading the documentation (https://llvm.org/docs/CommandGuide/llvm-mca.html) it also seems that llvm-mca does not take into account the cache hierarchy. Does this mean that the tool assumes all the loads/stores hit the L1 cache?

Looking forward to hearing from you.
Best regards,

Lorenzo Chelini.

(Adding Matt Davis, who should be able to help out here.)

Hi Lorenzo,

I’ll answer the first question you have:

I would like to use llvm-mca to estimate the IPC of a given code region. I am interested in the library version (https://reviews.llvm.org/D50929?id=162210) but I have troubles understanding how to use it. Could you please point me to some documentations or (better) some code examples if any?

The best example of the llvm-mca library being used is the actual llvm-mca tool itself. If you look in llvm/tools/llvm-mca/llvm-mca.cpp you’ll see that it is just a large program that uses the llvm-mca API and library. You’ll want to look at main() where the default pipline is created and the viewers are associated to that pipeline instance.

I read that out-of-order cores are supported. How about in-order cores? Would it be easy/difficult to add support for that?

Cheers,
Sjoerd.

Hi Sjoerd,

I read that out-of-order cores are supported. How about in-order cores? Would it be easy/difficult to add support for that?

Cheers,
Sjoerd.

I don’t think that it would be difficult to support in-order superscalar cores.
However, it would require a different llvm-mca pipeline of stages. That is because some stages (and simulated hardware components) work under the assumption that the processor is out-of-order (example: the dispatch stage and the retire stage).
That being sadi, it would be a bit more complicated to add support instruction itineraries. At the moment, the tool doesn’t understand itineraries.

If there is interest in supporting in-order cores, then we should probably raise a bug for it.

-Andrea

Hi Andrea,

We have quite a few Arm A-cores and also M-cores that would classify as in-order superscalars. I have been wanting to play with MCA for a while now, but never got round to it. I would be really interested in using it though. Just out of curiousity (I haven’t looked much into this), why are the instruction itineraries more important for in-order cores?

Cheers,
Sjoerd.

No worries, thanks for the info!

Sjoerd.

Hi,

I have just raised:
https://bugs.llvm.org/show_bug.cgi?id=41797 - MCA library document

https://bugs.llvm.org/show_bug.cgi?id=41796 - Add support for in-order processors

-Andrea