LLVM Newbie. Questions about backend.

I have been studying LLVM and started to create a new backend for a new RISC architecture. Now I need some help to get forward with my project. I'm quite new to compiling techniques so I'm sorry for the stupid questions.

Question 1:
My idea is to lower the select SDNode as follows:

%res1 = %falseVal
%res2 = setc %trueVal, %condition

Where setc is conditional mov. The question is how can I make sure that %res1 and %res2 are assigned to the same phsyical register? (I'm assuming you can only define virtual register once, is this correct assumption?)

Question 2:
What kind of information if any the front end needs about the target architecture? Am I able to use gcc front end to compile for the new architecture and what if there are 32- and 64-bit versions of the architecture? Is there an alternative front end and how does that handle the same issues?

Thank you very much in advance for your answers,


To use llvm-gcc, you’ll need to specifically enhance it with support for your architecture. llvm-gcc does much target-specific processing before and during LLVM IR codegen; its output is not at all portable.

In the LLVM IR, portable code is possible, but not guaranteed. llvm-gcc effectively never generates portable IR.

— Gordon

If you use a register constraint the existing infrastructure will take care of
this for you.

In your InstrInfo.td file you'll need something like this:

let Constraints = "$falseVal = $Rdest" {
def CMOV : YourTargetInst<
             (outs regclass$Rdest),
             (ins rc:$trueVal, rc:$falseVal, rc:$condition),
      "cmov $Rdest, $trueVal, $condition",
             [(set rc:$Rdest, (select rc:$condition, rc:$trueVal, rc:$falseVal))]>;