LLVM target-independent code generator for reconfigurable logic

hi every one,

i am use LLVM targeting a architecture with a processor and
reconfigurable logic around it.

now the llvm code generator work fine with the processor, but i am
struggling to make the code generator to generate proper DAGs for the
reconfigurable logic because "The LLVM target-independent code
generator is designed to support efficient and quality code generation
for standard register-based microprocessors.", so i want to insert my
special DAG building code to the code generator.

should i completely replace SelectionDAGISel, or modify
SelectionDAGISel when necessary like this:

LowerArguments(BasicBlock *LLVMBB) {
// code for traditional target
...........

  for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
       I != E; ++I, ++Idx) {

       if (TLI.isStrangeTarget()) {
             //code for my strange target
             TLI.HandleArgment(...);
             continue;
       }
       // code for traditional target
       .......
  }

    // code for traditional target
    .............

}

thank you for any suggestion

Hello Ether,

Yours isn't the first to target reconfigurable logic. I think http://www.c-to-verilog.com/ has a good example of going from a C compiler to reconfigurable logic. The usual way to lower to gate layout is to just lower the math operators to the equivalent use of an ALU and then optimize from there. Unfortunately for you, you'll need a modulo scheduler to make the code compile to raw gate layout with any reasonably acceptable level of optimization. Modulo schedulers are very processor intensive so you'll be adding minutes to the compile time and the results are only moderately good.

I hope this helps,

--Sam