LLVM with RISC-V V-extension intrinsic support

Hi,

We would like to announce that the RISC-V V-extension v0.10 has been implemented in LLVM and the work has been committed upstream.

Barcelona Supercomputing Center (BSC), Codeplay Software, and SiFive have worked together to implement the RVV C API intrinsics for the V-extension and have implemented the foundation of CodeGen for Vector Length Specific (VLS) and Vector Length Agnostic (VLA) autovectorization for RISC-V.

What we have committed to LLVM upstream:

Known issues:

  • C intrinsics for Zvlsseg implementation is under discussion:
  • What type we should use for fp16 is under discussion:

RISC-V RVV example:

https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv_saxpy.c

Build command:

clang --target=riscv64-unknown-elf -march=rv64gcv0p10 -menable-experimental-extensions rvv_saxpy.c -o rvv_saxpy.elf

Hi Kai,

Where can I find resources about the latest support for autovec for RISCV-V?

Hi,Kai, I’m a newer for riscv llvm, could you tell me where can i found the code or the relative description about the auto-vec part for the riscv llvm?