LLVM x86 backend for Intel MIC : trying it out and questions

Dear all,

I'm interested to analyse what could be done with current LLVM trunk
to deliver basic Intel MIC support. Let's say, for basic level we'd
want just scalar code execution, no threading, no zmm vectors.
Attached verbose in text, but functionally very simple patch
copy-pastes x86 and x86_64 backends into 32-bit and 64-bit K1OM. In
the end of the message you can find how simple LLVM-generated programs
could be compiled & executed on MIC device, using this patch.

Could you please help finding answers to the following questions:

1) Is there actually a 32-bit mode for MIC? 32-bit ELFs are not
recognized, so...
2) MIC ISA is 32-bit ISA (no SSE/MMX) plus 256-bit AVX-like vectors?
3) If 1 is "no" and 2 is "yes", then does MIC calling convention
permit generation of programs that use only 32-bit x86 ISA? In other
words, in common case, does calling convention require use of zmm
registers (e.g. return double value) even in scalar programs?

Thanks,
- D.

llvm.k1om.patch (20.9 KB)

Hello Dmitry,

I'm working on KNL backend and plan to push it to the open source once the ISA becomes public. We do not plan to support KNC architecture in open source.

- Elena

Hello Elena,

Thanks for info! Since Knights Landing (KNL) is going to be shipped
also in form of host CPU, it will have to have open-source support :slight_smile:
But given that KNL is only announced 1 month ago, we should expect up
to 1.5 years for it to become somewhat wide-spread, i.e. 2014-2015.
Meanwhile, I still hope to perform some KNC evaluation, so answers to
above questions are much appreciated!

Best,
- D.

1) Is there actually a 32-bit mode for MIC? 32-bit ELFs are not recognized, so...
There is no 32-bit KNC.

2) MIC ISA is 32-bit ISA (no SSE/MMX) plus 256-bit AVX-like vectors?
No, 256-bit vectors are not supported. KNC is scalar ISA (Knights Corner supports a subset of the Intel 64 Architecture instructions) + 512-bit vectors + masks

3) then does MIC calling convention permit generation of programs that use only 32-bit x86 ISA? In other words, in common case, does calling convention require use of zmm registers?
Please check what ICC does. X87 registers are supported.

- Elena

Hello Elena,

There is no 32-bit KNC.

Are you sure about this? From "System V Application Binary Interface
K1OM Architecture Processor Supplement Version 1.0", p. 124:

A.1 Execution of 32-bit Programs

The K1OM processors are able to execute 64-bit K1OM and also 32-bit

ia32 programs.

I'm really really looking for this opportunity, because we want to
extend our kernel code generation capabilities [1] with MIC support.

No, 256-bit vectors are not supported. KNC is scalar ISA (Knights Corner supports a subset of the Intel 64 Architecture instructions) + 512-bit vectors + masks

Of course, 512-bit, that was my typo, sorry.

Please check what ICC does. X87 registers are supported.

Checked. Unfortunately ICC does use zmm in scalar 64-bit programs,
which requires new ABI in LLVM.

- D.

[1] http://www.old.inf.usi.ch/file/pub/75/tech_report2013.pdf

32-bit code will work. ICC does not generate 32-bit KNC code. OS is 64-bit.

- Elena