Loop Vectorization and Store-Load Forwarding issue

I have been looking into this small test case (Part A) where loop vectorization is disabled due to possible store-load forwarding conflict (Part B). As you can see, due to the presence of dependence distance 2 the loop is vectorizable only for a width of 2. However, the presence of dependence distance 15 (due to y[j-15]) results in store-load forwarding issue as store packet of y[16:17] (iteration j=16) partially overlaps with load packets of y[15:16] (iteration j=30) and y[17:18] (iteration j=32). As conflicts introduce additional delays in the store->load forwarding pipes, this fact is modeled in the method MemoryDepChecker::couldPreventStoreLoadForward() in LoopAccessAnalysis.cpp. The function may turn off vectorization in the presence of such conflicts. Looking through the code gives me the feeling that it may be more conservative than desired. The reason being, if the dependence distance is high, the conflicting store may flush out of the store pipe by the time the load is issued. And vectorization may become beneficial.

I am seeing some performance improvements when I disable the method above. This is for x86. Hence I am seeking some advice on how to improve the following logic. Can we better model NumCyclesForStoreLoadThroughMemory ? This may be way too high ? Or there are other ways to circumvent the basic problem ?


Part A:
const unsigned NumCyclesForStoreLoadThroughMemory = 8*TypeByteSize; // 512 for the test case shown
// Maximum vector factor.
unsigned MaxVFWithoutSLForwardIssues = VectorizerParams::MaxVectorWidth * TypeByteSize;
if(MaxSafeDepDistBytes < MaxVFWithoutSLForwardIssues)
MaxVFWithoutSLForwardIssues = MaxSafeDepDistBytes;

for (unsigned vf = 2*TypeByteSize; vf <= MaxVFWithoutSLForwardIssues; vf *= 2) {
if (Distance % vf && Distance / vf < NumCyclesForStoreLoadThroughMemory) {
MaxVFWithoutSLForwardIssues = (vf >>=1);

if (MaxVFWithoutSLForwardIssues< 2*TypeByteSize) {
DEBUG(dbgs() << “LAA: Distance " << Distance <<
" that could cause a store-load forwarding conflict\n”);
return true;

Typo. The first sentence should read as:

… test case (Part B) where loop vectorization is disabled due to possible store-load forwarding conflict (Part C).


I’m seeing more cases where the compiler makes guesses about the processor rather than querying a machine model. Rather than a sophisticated model there could be a basic/lightweight machine description file that can be queried when it is available. In this specific example a formula like ‘dependence distance/ width > store2load_fwd_delay’ would help conflict modeling. Does that sound like a promising path forward?


Thx Gerolf. Let me investigate your suggestion.

I think this should be a call on TargetTransformInfo (TTI) similar to the instruction costs (TTI is a machine model). Targets can override this with the right value.

If we add a(nother) machine model we also have to implement the APIs to query it. I don’t think we would save complexity here and we add another model to maintain.

If we want have this in a description fiIe I think we should express in terms of the existing machine sched model. We could for example express this in terms of the existing load and store latencies and then have TTI query it through targetloweringinfo. Though I am not convinced that is necessary.