Lowering to mutiple independent instructions (RISC-V)

So I’m trying to convert a branch into mutiple instructions to do some research.

Original inst : beq $rs, $rt, target
New inst : bmov $bpr, target
bmov $bpr, $rs, $rt

Where bpr is some 256 bit reg and the first and second instructions write into different bit positions which I plan to model in some hw simulator.

It seems like multiple lowering is allowed only when there some is some chain where one instruction is used in the second one. In my case they’re independent so not sure how to lower them.
Another problem is that the branch selection node has no destination while my machine instruction(bmov) has one and that causes a matching issue as well.

There seem to be two options with either pseudo instructions or DAGtoDAG but not sure how that works as I’m new to LLVM. Would appreciate some help!

That’s not a branch?

So the idea is to replace the beq with writes to the bpr register and then the simulator will take care of the actual jump to target based on contents of the bpr