Machine scheduler issue

Hi all,
I’m currently building a vliw port based on a llvm 3.5.0 from 2014, where I have enabled the MachineScheduler to run bottom up. I see that there is an issue with respect to the moment when instructions move from
pending to ready. Namely instructions which should still be pending become ready too early
such that I end up with true dependent instructions being issued at the same cycle.
I think the issue comes from ScheduleDAGMILive::schedule() function. Inside it the updating of the queues
happens before SchedImpl->schedNode(SU, IsTopNode) is being called while should have happened after.
See bellow the code fragment where perhaps the call from 1020 should be after line 1032:

1020: updateQueues(SU, IsTopNode); if (DFSResult) { unsigned SubtreeID = DFSResult->getSubtreeID(SU); if (!ScheduledTrees.test(SubtreeID)) { ScheduledTrees.set(SubtreeID); DFSResult->scheduleTree(SubtreeID); SchedImpl->scheduleTree(SubtreeID); } } // Notify the scheduling strategy after updating the DAG. 1032: SchedImpl->schedNode(SU, IsTopNode);

The MachineScheduler.cpp file that I use in my port you can see here:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_35/lib/CodeGen/MachineScheduler.cpp?revision=215011&view=markup

For oo machines the issue that I observe wont trigger a bug but in my case as im porting llvm
to a vliw (where i produce bundles) instructions becoming ready too early leads to incorrect code.

thanks,
Alex