I am trying to modify the RISCV backend of LLVM compiler. I would like to reserve a few registers and used them to mask the target of jump/load instructions. The reserved registers will be set by some loader code.
Before every load/store or branch instruction, I want to check if the address is in bounds by masking their destination with the masks that will be stored in the registers that were reserved. These registers will be initialized by an initial loader code and should never be changed afterward (hence reserved). As an example, the following instruction:
jalr rd, rs, imm
should be replaced by:
addi t1, rs, imm
and t1, t1, s2 // s2 is one of the reserved registers
jalr rd, t1, 0
I tried looking in the tabelgen files and RISCV interfaces like RISCVISelLowering, RISCVISelDAGtoDAG, InstPrinter, etc. Can anyone suggest where should I try making changes to get the desired effect or point me to some documentation or code examples?