Matching patterns

I'm trying to create a TableGen pattern to match extract_vector_elt.
My pattern looks like this:

    (set i32:$dest, (extract_vector_elt v16i32:$src, i32:$index))

However, when I compile, I get an error:

    error: Variable not defined: 'extract_vector_elt'

However, if I omit the rule and attempt to compile something that uses
this functionality with clang, I get this error, which is definitely
using the name 'extract_vector_elt':

LLVM ERROR: Cannot select: 0x7fc6c402a110: i32 = extract_vector_elt
0x7fc6c402a410, 0x7fc6c4029e10 [ORD=10] [ID=10]
  0x7fc6c402a410: v16i32,ch = load 0x10480ebb8, 0x7fc6c402a010,
0x7fc6c402a310<LD64[%1]> [ORD=8] [ID=8]
    0x7fc6c402a010: i32,ch = load 0x10480ebb8, 0x7fc6c4029c10,
0x7fc6c402a310<LD4[%value.addr]> [ORD=7] [ID=5]
      0x7fc6c4029c10: i32 = FrameIndex<0> [ORD=7] [ID=1]
      0x7fc6c402a310: i32 = undef [ORD=7] [ID=2]
    0x7fc6c402a310: i32 = undef [ORD=7] [ID=2]
  0x7fc6c4029e10: i32,ch = load 0x10480ebb8, 0x7fc6c402a810,
0x7fc6c402a310<LD4[%i]> [ORD=9] [ID=6]
    0x7fc6c402a810: i32 = FrameIndex<2> [ORD=9] [ID=3]
    0x7fc6c402a310: i32 = undef [ORD=7] [ID=2]

This is an area that has been confusing for me in general for a while.
In many cases, the name of the instruction pattern is the same as the
LLVM IR instruction, for example, 'and'. In other cases, it is
slightly different. For example the 'select_cc' IR instruction seems
to match the rule 'selectcc' in several of the backends. And in some
other cases, like extract_vector_elt, there doesn't seem to be an
equivalent named rule. I've reread the instruction selection section
of the docs several times and this is still not clear to me. Is there
a place in the code to look to find the mappings, or am I missing
something more fundamental?

Hi Jeff,