MC Assembler / tablegen: actually parsing variable_ops

variable_ops is used in the tablegen defs for many targets to denote instructions that a variable number of inputs, but it seems that there aren’t any targets for which this results in variable elements in the instruction encoding (and thus in assembler parsing), since the tablegen generated assembly matcher ($(Target)GenAsmMatcher.inc) simply assumes that variable_ops are not to be parsed (match table: Convert_NoOperands).

Now I understand that a variable length instruction is a weird concept for most CPUs, but we need it for at least one instruction in WebAssembly. We can probably hack around it in the WebAssemblyAsmParser, but I wonder if there’s something I am not understanding about variable_ops and the generated asm matcher that might make for a cleaner solution.

The instruction in question: https://github.com/llvm-mirror/llvm/blob/master/lib/Target/WebAssembly/WebAssemblyInstrControl.td#L45

ARM has ldm/stm, which take a variable number of register operands. You might want to look at how ARMInstrInfo.td uses a "reglist" operand to represent the list of registers.

-Eli

Thanks! I’m adopting what ARM does for WebAssembly, and it appears to work well.
https://reviews.llvm.org/D55401