Meaning of hasSideEffects bit

The tablegen files that describe backends use the

 hasSideEffects

bit to classify instructions. [1] is an example of an X86 instruction setting this bit to 0. What exactly does side-effect mean in this context? It seems to go beyond main-memory effects, for example in RISCV this bit is set for FENCE and CSR instructions, e.g. [2]. Is each target free to define this bit or is it target independent?

[1] TableGen Overview — LLVM 16.0.0git documentation

[2] https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/RISCV/RISCVInstrInfo.td#L607-L610

correct, as the comment of this field suggested, you should set this field whenever an instruction changes something that is not captured by the operands.

This is one of the instruction properties so each target is free to setup this flag on a per-instruction basis.

It’s a catch all for things that aren’t modeled properly. It’s not super well defined.

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So in other words, there is no behaviour in the target independent part of code-gen that depends on this flag?

No; search for MachineInstr::hasUnmodeledSideEffects. For example, it affects MachineLICM.

@jrtc27 But this relates to InlineAsm::Extra_HasSideEffects which does not seem to be related to hasSideEffects. Maybe I’m overlooking the connection between the two?

That’s only part of it. It also checks MCID::UnmodeledSideEffects, which is what hasSideEffects is mapped to by TableGen.

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