Memory dependence around read-modify-write instructions

Code Generation Common Infrastructure
#1

Our arch has 8 and 16 bit stores that do a read-modify-write on 32 bit. This means that we need to specify a latency between two such instructions that may touch the same memory.
I will usually have an output dependence edge that I can find to ‘dagmutate’ the latency, fine.

I’m afraid that alias analysis may be able to disambiguate based on constant offset differences between accesses on the same object, losing me that output edge.
I’d like to tell dependence analysis that these stores access 32 bit.
I have marked the instruction to be both a load and a store; ultimately I would like to specify different load and store bitwidths as well.

My question: What is the best way to widen the access width of loads and stores from the default?

#2

FYI: it’s not too difficult to change the access size in the memory operand in global isel. My problem is that the effective offset should also be changed to the word boundary, and for that I need to fix the LLVM value for the base address. I’m not sure whether I’m supposed to touch the LLVM IR during instruction selection.

#3

Current plan: do a search for the base address in the LLVM Value, collecting constant offsets on the way. Modify the memoperand to use that base address and accumulated offset. I’m assuming that non-constant offsets to the same base address will also put off alias analysis, in particular since I lose any tbaa info brought in by the address modifiers. I’ll not be modifying LLVM IR.