MemRefs in a Load Instruction

Hi,

On the hexagon target, I have written a following combiner pattern.

From: llvmdev-bounces@cs.uiuc.edu [mailto:llvmdev-bounces@cs.uiuc.edu]
On Behalf Of Pranav Bhandarkar
Sent: Thursday, April 26, 2012 5:24 PM
To: llvmdev@cs.uiuc.edu
Subject: [LLVMdev] MemRefs in a Load Instruction

Hi,

On the hexagon target, I have written a following combiner pattern.
*********************************************

def: Pat<(i64 (or (i64 (shl (i64 (extloadi32 (i32 (add IntRegs:$src1,

s11_2ExtPred:$offset1)))),
                                                            (i32 32))),
                                    (i64 (zextloadi32

ADDRriS11_2:$src2)))),

         (i64 (COMBINE_rr (LDriw_indexed IntRegs:$src1,
s11_2ExtPred:$offset1),
                                               (LDriw

ADDRriS11_2:$src2)))>;

******************************

I had to modify the above pattern where in the LDriw (the second load in the
COMBINE_rr) is changed to LDriw_indexed similar to the first load.
I see the following in HexagonGenDAGISel.inc

From: llvmdev-bounces@cs.uiuc.edu [mailto:llvmdev-bounces@cs.uiuc.edu]
On Behalf Of Pranav Bhandarkar
Sent: Thursday, April 26, 2012 8:01 PM
To: llvmdev@cs.uiuc.edu
Subject: Re: [LLVMdev] MemRefs in a Load Instruction

> From: llvmdev-bounces@cs.uiuc.edu [mailto:llvmdev-
bounces@cs.uiuc.edu]
> On Behalf Of Pranav Bhandarkar
> Sent: Thursday, April 26, 2012 5:24 PM
> To: llvmdev@cs.uiuc.edu
> Subject: [LLVMdev] MemRefs in a Load Instruction
>
> Hi,
>
> On the hexagon target, I have written a following combiner pattern.
> *********************************************
>
> def: Pat<(i64 (or (i64 (shl (i64 (extloadi32 (i32 (add IntRegs:$src1,
>
> s11_2ExtPred:$offset1)))),
> (i32 32))),
> (i64 (zextloadi32
ADDRriS11_2:$src2)))),
> (i64 (COMBINE_rr (LDriw_indexed IntRegs:$src1,
> s11_2ExtPred:$offset1),
> (LDriw
ADDRriS11_2:$src2)))>;
> ******************************

I had to modify the above pattern where in the LDriw (the second load in

the