Mips -> DLX Modifications as Target

Hello,

Past few days I have been working on a DLX Target for LLVM using the
Mips Target as a base.

Coming along quite well, currently ran into two problems with my
sample/test program.

The main issue I am having is with respect to the following
(Note: I have already changed ADDui from ADDiu)

We have this
def ADDui : ArithI<0x09, "addui", add, simm16, immSExt16>;
However sticky speaking this should be in dlx the instructions are
addui rk, ri, Kuns (Where Kusn is unsigned)

Likewise DLX has a subui rk, ri, Kusn. (Mips does not)

Thus they should be:
def ADDui : ArithI<0x09, "addui", add, simm16, immZExt16>;
def SUBui : ArithI<0x23, "subui", sub, simm16, immZExt16>;

However I am not sure how or where to setup in the Target Descriptor
of the Instructions or (even the .cpp) to get it
to support 16-bit sign constants that that are negative to map to the SUBui.

Doing the above change (S -> Z) for addui means it activates a later
pattern which causes it to instead of doing
addui r2, r4, -5 it will do addi r2, r0, -5 then addu r2, r4, r2
(which of course is equivalent) but would be better just to do
subui r2, r4, 5.

Mainly the problem is if the constant is specified as negative, and
when 0-constant can fit in 16-bits unsigned, wish it to use the SUBui
instruction.

Sorry if this is hard to understand but any piece of help in fixing
this is very much appertained.

If it helps I am using the source for llvm 2.5 as a base.

Regards,
Sean Donno

Hello, Sean

Mainly the problem is if the constant is specified as negative, and
when 0-constant can fit in 16-bits unsigned, wish it to use the SUBui
instruction.

sub reg, imm is canonicalized in LLVM into add imm, -imm. You need to
"replay" this back via some "pipehole" pattern.

You might find ARM target useful as an example.