MIPS Register Pressure Limit.

Hello,
why LLVM does not define physical register limits for MIPS by overriding the TargetRegisterInfo::getRegPressureLimit function the way it’s done for X86 in x86RegisterInfo.cpp and ARM.

Thanks in advance.

Jafar,

The getRegPressureLimit hook is still used by the current SelectionDAG instruction scheduler. If that’s what you care about, then you need to implement it manually. But there is a new pair of hooks that are now generated automatically for you (pasting bits of MipsGenRegisterInfo.inc below.) You can use these hooks directly. The API is raw because it currently only supports a register tracker utility, but I’ll take feedback for improving the API. If you do need the old manual hook, then you can implement it in terms of these auto-generated ones.

-Andy

// Get the register unit pressure limit for this dimension.
// This limit must be adjusted dynamically for reserved registers.
unsigned MipsGenRegisterInfo::
getRegPressureSetLimit(unsigned Idx) const {
static const unsigned PressureLimitTable[] = {
32, // 0: CPURegs
32, // 1: FGR32
8, // 2: CPU16Regs
2, // 3: HILO
1, // 4: CCR
1, // 5: CPURAReg
1, // 6: HWRegs
1, // 7: HWRegs64
0 };
return PressureLimitTable[Idx];
}

/// Get the dimensions of register pressure impacted by this register class.
/// Returns a -1 terminated array of pressure set IDs
const int* MipsGenRegisterInfo::
getRegClassPressureSets(const TargetRegisterClass *RC) const {
static const int RCSetsTable[] = {
0, -1, // CPURegs
1, -1, // FGR32
0, 2, -1, // CPU16Regs
3, -1, // HILO
4, -1, // CCR
0, 5, -1, // CPURAReg
6, -1, // HWRegs
7, -1, // HWRegs64
0, -1, // CPU64Regs
1, -1, // FGR64
1, -1, // AFGR64
0, 2, -1, // CPU64Regs_with_sub_32_in_CPU16Regs
3, -1, // HILO64
0, 5, -1, // CPU64Regs_with_sub_32_in_CPURAReg
-1 };
static const unsigned RCSetStartTable[] = {
0,2,4,7,9,11,14,16,18,20,22,24,27,29,0 };
unsigned SetListStart = RCSetStartTable[RC->getID()];
return &RCSetsTable[SetListStart];
}