Misaligned SSE store problem (with reduced source)

Using LLVM 2.9, the following LLVM IR produces invalid x86 32 bit assembly (a misaligned SSE store).

; ModuleID = ‘MisalignedStore’

define void @MisalignedStore() nounwind readnone {
entry:
%v = alloca <4 x float>, align 16
store <4 x float> zeroinitializer, <4 x float>* %v, align 16
br label %post-block

post-block:
%f = alloca float
ret void
}

If I feed this to llc with -march=x86, the following is produced. Note the 24 byte offset from ebp:

.def _MisalignedStore;
.scl 2;
.type 32;
.endef
.text
.globl _MisalignedStore
.align 16, 0x90
_MisalignedStore: # @MisalignedStore

BB#0: # %entry

pushl %ebp
movl %esp, %ebp
subl $24, %esp
pxor %xmm0, %xmm0
movaps %xmm0, -24(%ebp)
movl $8, %eax
calll __alloca
movl %ebp, %esp
popl %ebp
ret

The code is trivial and useless, but it’s a boiled down version of a real program. Am I doing something wrong in that IR? Note that removing the last alloca of %f or the jump to post-block both cause the resulting assembly to be correct. Note also that specifying -march=x86-64 to llc results in correct code as well. If this is a known problem and has been fixed already, can you point me at the commit?

Aaron Dwyer
Imagination Technologies

It's a known issue that the x86 backend doesn't know how to generate
dynamic stack realignment code for functions using allocas outside the
entry block. Don't know the bug number off the top of my head.

-Eli

Eli thanks very much for the response! I guess I'll work on raising all my allocas up to my function entry blocks and this should be resolved. Cheers!

Aaron

These ones look relevant:

http://llvm.org/bugs/show_bug.cgi?id=2962
http://llvm.org/bugs/show_bug.cgi?id=4422

Jay.

Both of those look reasonable yes.

-eric