I am looking at the Hexagon MI Scheduling and trying to adapt it to my target.
As far as I can see, Hexagon does not bundle the VLIW-bundles by calling bundleWithPred() on MIs of the completed cycle.
First of all, why is this not done? SlotIndexes seems to have at least some support for this, by calling getBundleStart() for each MI that is looked up.
A follow up question is then, how would I do this, so that the register allocator can work with bundle intervals?
Just calling bundleWithPred() gives
*** Bad machine code: Instruction inside bundle has a slot index ***
I would really appreciate if anyone let me know the plan on this,
Ø As far as I can see, Hexagon does not bundle the VLIW-bundles by calling bundleWithPred() on MIs of the completed cycle.
You are right as of now. The reason is purely historical. At the point of VLIW MI scheduler (aka Hexagom MI scheduler) creation bundleWithPreds was not yet available and most passes after the MI sched could not handle bundled code. In fact you can see that VLIW scheduler does form temporary bundles, but then simply throws them away. This only preserves order of instructions until the later bundle formation.
It all will change. The goal is to have bundles formed at the MI sched time and keeping them throughout the rest of compilation. Note that this might involve occasional dissolution of a bundle, which might not always be possible.
If you want to use the process Hexagon uses now, bundle formation takes place after the second pass scheduling, and if you have specific questions about it, I can try to answer them.
Hope this helps.