# MLIR Sparse Compiler Progress

**URL:** <https://discourse.llvm.org/t/mlir-sparse-compiler-progress/60479>\
**Category:** MLIR\
**Created:** [February 24, 2022, 2:22am UTC](https://discourse.llvm.org/t/mlir-sparse-compiler-progress/60479 "2022-02-24T02:22:59Z")\
**Posts on this page:** 1\
**Showing post:** 12

<div class="post-metadata">

**Author:** ![aartbik](https://sea1.discourse-cdn.com/flex021/user_avatar/discourse.llvm.org/aartbik/32/316_2.png) [@aartbik](https://discourse.llvm.org/u/aartbik)\
**Post date:** [November 18, 2022, 9:51pm UTC](https://discourse.llvm.org/t/mlir-sparse-compiler-progress/60479/12 "2022-11-18T21:51:43Z")

</div>

For our good friends at ARM, I also dotted a few i’s in the revision to make sure scalalabe vectors (ArmSVE) keep working! Here is a reduction example.

```auto
    %2 = memref.load %1[] : memref<f32>
    %3 = vector.vscale
    %4 = arith.muli %3, %c4 : index
    %5 = vector.insertelement %2, %cst[%c0 : index] : vector<[4]xf32>
    %6 = scf.for %arg3 = %c0 to %c1024 step %4 iter_args(%arg4 = %5) -> (vector<[4]xf32>) {
      %9 = affine.min #map2(%c1024, %arg3)[%4]
      %10 = vector.create_mask %9 : vector<[4]xi1>
      %11 = vector.maskedload %0[%arg3], %10, %cst : memref<?xf32>, vector<[4]xi1>, vector<[4]xf32> into vector<[4]xf32>
      %12 = arith.addf %arg4, %11 : vector<[4]xf32>
      %13 = arith.select %10, %12, %arg4 : vector<[4]xi1>, vector<[4]xf32>
      scf.yield %13 : vector<[4]xf32>
    }
    %7 = vector.reduction <add>, %6 : vector<[4]xf32> into f32
    memref.store %7, %1[] : memref<f32>

```

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_[View the full topic](https://discourse.llvm.org/t/mlir-sparse-compiler-progress/60479)._