MnemonicAliases and side-effects

Hello!

I have a question about Instructions and MnemonicAliases.

Let's say I have an instruction (an instruction prefix actually, in
the X86 backend), and the instruction has 'Defs' and 'Uses' defined
for it.
If I define a MnemonicAlias from that instruction prefix to another,
then do the 'Defs' and 'Uses' get "applied" to the alias as well?

In other words, is it possible to define two instruction prefixes with
the same "opcode" such that one prefix defines 'Defs' and 'Uses' while
the other does not.

Thanks!

- Muhammad Tauqir

Short answer: No, that's not how assembly aliases work.

A MnemonicAlias is entirely a construct of the assembly parser. By the time anything that matches via the alias gets to parts of the toolchain that know anything about uses and defs, it's as-if there only ever were one instruction definition at all.

-Jim

Thanks for the answer.

So for my second question:

In other words, is it possible to define two instruction prefixes with
the same "opcode" such that one prefix defines 'Defs' and 'Uses' while
the other does not.

Is this possible? If yes, how can it be done? And can one be enabled
or disabled based on some processor features? I can't seem to be able
to figure out a way to do it.

- Muhammad Tauqir