Modelling multiple-issue micro-architectures for specific instr pairs

Hi there,
I’m trying to model multiple-issue in an ARM subtarget. This micro-architecture expects that some instruction pairs are allowed to be issued together, but not in the reverse order (i.g. shift+mov can be multiple-issued, but no multiple-issue for mov+shift).

Currently I have not found any solution yet to model this behaviour. Is there any known solution that allows to model the multiple-issue for specific pairs of instructions?

Thanks in advance.