Modelling registers per subtarget

For my toy architecture, I have two subtarget, target 1 and target 2. Target 1 has 1024 and Target2 has 2048 GPRs. How do I model them in .td files? Should I just create a RegisterClass for them? If so, how do I associate them with SubtargetFeature or ProcessorModel?

If this is not the right way then can someone please educate?



I could be wrong but the register hierarchy doesn’t really take into account subtargets, instead you can, like you said, create different register classes for them, then have different sets of instructions for each of the subtarget (e.g., take a look at how GR16 vs. GR16_NOREX are modeled in X86).

Now assuming target2 is a strict super set of target1, there is actually a simpler approach:

  • Have one register class for all 2048 gprs
  • Mark the 1024 top gprs as not “reachable” for target1

You could do that by simply modifying TargetRegisterInfo::getReservedRegs.

Note: even if you use the register class approach with different instructions, you’ll need to modify that function to “disable” the top registers for target1 anyway. Otherwise you may end up with “out-of-bound’ registers (w.r.t. target1) in things like copies.

Take a look at X86RegisterInfo::getReservedRegs for instance.


Ideally, I’d expect this to be a part of ProcessorModel or Processor in Logically, a Processor(Model) is a group of chip-specific things and registers should not be an exception here.
On the other side of what Quentin said, the two subtargets could be mutually exclusive from a register file perspective and even register names could be different.

So, I’d expect programmers to create two different RegisterClasses and “associate” them with the Processor(Model).
IMHO, this modular design allows separation of concern and composability for subtargets.

However, it does not seem so.

I think that similarly to what Quentin suggested, it is very straightforward to define the full register class and use AltOrders and AltOrderSelect in the definition of the register class.
The alternate allocation order would be just the 1024 registers and the selector would be just a check of the subtarget.