MOS6502 target


As an old Commodore 64 bedroom-coder, I've got a few good ideas for optimization in your 6502 compiler.

The first rule is like this: an array of any multibyte structures is slower than a structure of multiple arrays of byte-long elements. In other words, use byte-planes instead of actual contiguous structures if at all possible. This will practically eliminate the need for most usage of the indexed-indirect addressing mode (y-indexing off a zero-page address-pair-pointer) because each array will start at a non-relocatable absolute address and use either x or y as the index. The limitation of this optimization is that it requires that there be an array dimension between 1 and 256 elements. An example of this is that a 16-bit integer is a multibyte structure of a high-byte and a low-byte. To make a 128 element array of 16-bit integers you convert it to two 128-element arrays of bytes: an array of high-bytes and an array of low-bytes. This also eliminates the need for multiplying indexes by a scale factor based on the size of the element because in a byte-plane each byte is 1 unit in length, essentially allowing you to multiply only by 1.

The second rule is a suggestion: address the zero-page as 128 general-purpose registers of 16-bits each that can be subdivided into 2 subregisters of one byte each. Zero page is used mostly in 16-bit aligned pairs for pointer contents when indexed-indirect addressing cannot be avoided. In the same way in the early Intel 8086 machines (whose legacy is still recognized in modern x86 chips), the AH and AL subregisters constituted the high-byte and low-byte contents of the AX register.

Blessings on you for making an 8-bit compiler!