Multiple-Pipeline Itinerary

Is there a way to express a multiple pipeline itinerary using the
current scheme (maybe some trick with setting NextCycles = 0)?
Specifically, consider a case where a floating-point load simultaneously
uses units from a floating-point pipeline and a load/store pipeline.

Thanks in advance,
Hal

Is there a way to express a multiple pipeline itinerary using the
current scheme (maybe some trick with setting NextCycles = 0)?
Specifically, consider a case where a floating-point load simultaneously
uses units from a floating-point pipeline and a load/store pipeline.

To be clear, in my parenthetical above, I mean setting TimeInc (which
says, "cycles till start of next stage") = 0.

-Hal

Hello Hal.

Is there a way to express a multiple pipeline itinerary using the
current scheme

Yes, surely

(maybe some trick with setting NextCycles = 0)?

Yep!

Specifically, consider a case where a floating-point load simultaneously
uses units from a floating-point pipeline and a load/store pipeline.

Look into ARM itineraries, they contain a decent amount of such examples.

Anton,

Thanks!

What is the difference between Reserved and Required?

-Hal

Hal,

What is the difference between Reserved and Required?

Think about them like read/write locks.

E.g. if FU is Reserved (=read lock) is can be Reserved multiple times,
but never Required.
If FU is Required (=write lock) it cannot be neither Reserved nor Required.

In the example provided:

// InstrItinData<IIC_iLoad_i , [InstrStage<1, [A9_Pipe1]>,
// InstrStage<1, [A9_AGU]>],
// [3, 1], [A9_LdBypass]>,

If there is an operand dependency, does the scheduler assume that the
instruction is held in A9_Pipe1 or in A9_AGU until the operand is ready?

Thanks again,
Hal

Hi Hal,

// InstrItinData<IIC_iLoad_i , [InstrStage<1, [A9_Pipe1]>,
// InstrStage<1, [A9_AGU]>],
// [3, 1], [A9_LdBypass]>,

If there is an operand dependency, does the scheduler assume that the
instruction is held in A9_Pipe1 or in A9_AGU until the operand is ready?

Yes. Watch these [3, 1] numbers. Basically it's the number of cycles
until the result ir ready (for output operands) or cycle # when the
operand is read (for input operands)