New floating-point ISA for AI needs compiler

Dear LLVM Developers,

Developed using the “free” version of XILINX Vivado and targeted for implementation in their Kintex Ultra-class FPGAs, I’ve recently developed an new universal floating-point ISA computer that can compute DIRECTLY with human-readable decimal character sequences (up to 28 decimal digits in length) and/or binary formats in any combination. It is written in Verilog RTL and implements in hardware ALL operations mandated by IEEE 754-2008 requiring only one instruction per operation. It’s mainly intended for web-based AI, NN, DL kinds of things. This new ISA does not employ “opcodes.” It does, however, include a REPEAT operator and auto-post-modify indirect addressing mode, among others. There are only four mnemonics.

The purpose of this communication is to let you know about the above ISA and to see if anyone would be interested in targeting LLVM for this new ISA. Below are links to the documentation on the new ISA, including the instruction table for use with a popular universal cross-assembler.

Universal floating-point ISA written description and Figures:

https://drive.google.com/file/d/1Vu0urSXxnTgXaMd5V7PhKCptc26lE6rD/view

Instruction table for use with Cross-32 Universal Cross Assembler:

https://drive.google.com/file/d/1yEII3NNUGfu4oM_o47cKpWXC812WXlpK/view

I thank you in advance for your time and kind consideration.

Yours very truly,

Jerry