Newbie: Target Lowering info.

Could anybody guide me what information do I need to know about my
target in order to provide the target lowering info to the llvm DAG
generator? We do not have any fixed registers for argument passing.
Everything including the formal and actual arguments will take part in
a global interprocedural regalloc.

Any pointers to learn about this will be a great help.
Sanjiv

Could anybody guide me what information do I need to know about my
target in order to provide the target lowering info to the llvm DAG
generator? We do not have any fixed registers for argument passing.
Everything including the formal and actual arguments will take part in
a global interprocedural regalloc.

You don't have to formally specify calling convention. For example, ARM backend does not have a ARMCallingConv.td file, all the argument passing info are implicitly defined in the lowering code.

To start, you should specify legal register files, legal operations, etc. See XXXISelLowering.cpp for examples.

Evan

thanks Evan,
I have just started writing td files.

Any ideas how do I describe instructions for an accumulator based machine.
The other pecularity is that we do not want to have any software stack.
So the instructions like load and store have no meanings.

In that case, how do I lower instructions that operate on stack frame?

TIA,
Sanjiv

thanks Evan,
I have just started writing td files.

Any ideas how do I describe instructions for an accumulator based machine.

That is tricky. It doesn’t really fit the LLVM codegen model. One thing you can do is to add pseudo registers to allow “normal” register allocation. Then you can add a post pass to convert everything to stack operation. That’s how we handle x87 floating point math. The model is not an exact match to an accumulator based model, but it’s an idea.

You will probably also need to tweak the instruction scheduler to get better code later.

The other pecularity is that we do not want to have any software stack.
So the instructions like load and store have no meanings.

Not sure what you mean by load and store have no meanings?

In that case, how do I lower instructions that operate on stack frame?

LLVM codegen has a frame index representation. They are created during lowering pass and during register allocation. The prologue and epilogue elimination pass will then translate them using explicit stack pointer, etc.

Evan