Nontemporal memory accesses and fences

The current specification of the behavior of the !nontemporal attribute in LLVM, and the _builtin_nontemporal* functions in Clang, is rather spartan and underspecified. In effect, it says the following things:

  • Atomic !nontemporal has no defined semantics
  • !nontemporal may use special instructions to save cache bandwidth, such as “MOVNT” on x86.

What is crucially lacking from this specification is its effects in relation to other memory ordering constructs, namely fences. In lieu of text to the contrary, one could reasonably come to the conclusion that this code should be sufficient to generate correctly working code:

store i64 %x, i64* %addr, !nontemporal !100

fence release

But on x86 today, it does not: the first store is lowered to a MOVNT, while the fence release is lowered to a compiler-only memory barrier instead of an SFENCE (as regular load/store/atomicrmw operations already have these operations built into their execution semantics). So the fence instructions appear to be lowered with the expectation that nontemporal instructions do not exist, which is not implied by the language reference.

I’ve been pointed to an earlier thread (https://lists.llvm.org/pipermail/llvm-dev/2016-January/093912.html) that suggests an introduction of nontemporal-specific fences, but there appears to have been no effort to actually push this into LLVM. What’s the current status of this work, and what is the right way to move forward and clarifying the semantics of !nontemporal with respect to threads.

I see nontemporals as a nice builtin so you don’t have to hand-write the assembly. I don’t think existing hardware is consistent enough to allow us to expose nice semantics at a language or IR level, in the sense that we probably don’t want to define what happens if you step out of the comfortable uses for nontemporals (i.e. what happens when you start having temporality). A builtin pre / post fence seems fine to me, but that still leaves a gaping semantic hole… which I’m also fine with.

FWIW you have the same problem, somewhat worse, with some vector load / store instructions on some ISAs.

I was under the impression that we had decided to move forward with the fence, and it continues to make sense to me.

-Hal

I was under the impression that we had decided to move forward with the fence, and it continues to make sense to me.

I probably missed a prior discussion, so a link would be great! That being said, fences sound fine to me as long as they’re “nice builtins instead of inline asm” and don’t try to offer more than “whatever the hardware instruction, if any, means”.

I was referring to your RFC linked below (from 2016). We might also have talked about this offline. The fences seemed like a sensible solution. Reviewing the RFC thread, it seemed like: 1) We needed separate load and store fences and 2) There may have been some uncertainty how to map these on ARM.

-Hal

I was referring to your RFC linked below (from 2016).

Ah gotcha! My memory is failing me and I didn’t remember specifics.

We might also have talked about this offline. The fences seemed like a sensible solution. Reviewing the RFC thread, it seemed like: 1) We needed separate load and store fences and 2) There may have been some uncertainty how to map these on ARM.

Sounds about right :slight_smile: