Operands Not processed Assert

I have architecture in which only legal type supported in i64.

So inside getCopyToParts() function. when ValueVT=f32 and PartVT==i64
I added code to handle this condition inside
if(NumParts * PartBits > ValueVT.getSizeInBits()) block
as follows:

if(ValueVT == EVT(MVT::f32) && PartVT == MVT::i64){
    SDValue IntMVal = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f64, Val);
    Val = DAG.getNode(ISD::BITCAST, DL, PartVT, IntMVal);
}

And inside getCopyFromParts() function at the end I added:
if(ValueVT == EVT(MVT::f32)) {
    SDValue IntMVal = DAG.getNode(ISD::TRUNCATE, DL, EVT(MVT::i32), Val);
return DAG.getNode(ISD::BITCAST, DL, ValueVT, IntMVal);
}

After giving -debug to llc, in Optimized lowered selection DAG phase I get
sequence:

                  0x21103e0: i64,ch = CopyFromReg 0x20d86e0, 0x210e6b0
[ORD=4]

                0x210e7b0: i32 = truncate 0x21103e0 [ORD=4]

              0x2110ce0: f32 = bitcast 0x210e7b0 [ORD=4]

              0x210ffd0: f32 = ConstantFP<1.000000e+00>

            0x210e5b0: f32 = fadd 0x2110ce0, 0x210ffd0 [ORD=4]

          0x210f7d0: f64 = fp_extend 0x210e5b0 [ORD=4]

        0x210f3d0: i64 = bitcast 0x210f7d0 [ORD=4]

      0x210deb0: ch = CopyToReg 0x20d86e0, 0x21106e0, 0x210f3d0 [ORD=4]

after this llc fails in Legalizer:

"Operand not processed?
0x210deb0: ch = CopyToReg 0x20d86e0, 0x21106e0, 0x2125d30 [ORD=4] [ID=1]
"

with third operand of CopyToReg some garbage value.
What am I doing wrong ?

Thanks,
Akhsay.