http://llvm.org/docs/CodeGenerator.html#machine-code-description-classes
Section starting:
Fixed (preassigned) registers
It talks about converting:
define i32 @test(i32 %X, i32 %Y) {
%Z = udiv i32 %X, %Y
ret i32 %Z
}
into
;; X is in EAX, Y is in ECX
mov %EAX, %EDX
sar %EDX, 31
idiv %ECX
ret
BUT, where does the "sar" come from?
Kind Regards
James
idiv divides (%EDX:%EAX) by it's argument (%ECX). As the code have only
32-bit argument it needs to be bit extended from %EAX to %EDX:%EAX.
sar is arithmetic shift right so sar %EDX, 31 copy the bit sign to all
bits of register.
> http://llvm.org/docs/CodeGenerator.html#machine-code-description-classes
>
> Section starting:
>
> Fixed (preassigned) registers
>
> It talks about converting:
>
> define i32 @test(i32 %X, i32 %Y) {
> %Z = udiv i32 %X, %Y
> ret i32 %Z
> }
>
> into
>
> ;; X is in EAX, Y is in ECX
> mov %EAX, %EDX
> sar %EDX, 31
> idiv %ECX
> ret
>
> BUT, where does the "sar" come from?
>
> Kind Regards
>
> Jamesidiv divides (%EDX:%EAX) by it's argument (%ECX). As the code have only
32-bit argument it needs to be bit extended from %EAX to %EDX:%EAX.sar is arithmetic shift right so sar %EDX, 31 copy the bit sign to all
bits of register.
There's actually an instruction designed just for doing this: CDQ (although
on modern uarches it's probably not a performance win; regardless, the
latency of the IDIV will dwarf the cost of the sign extension).
-- Sean Silva
idiv divides (%EDX:%EAX) by it's argument (%ECX). As the code have only
32-bit argument it needs to be bit extended from %EAX to %EDX:%EAX.sar is arithmetic shift right so sar %EDX, 31 copy the bit sign to all
bits of register.
That makes sense for sdiv (though we seem to use the cltd these days),
but the documentation does say "udiv". I've committed r199092,
correcting the sign and making it a hypothetical scenario since we
don't actually produce that code any more.
Thanks for telling us about this Maciej.
Cheers.
Tim.