Hello, I’ve noticed the following issue while testing some codegen tests, i would like to know if it’s a missed optimization or i missed something out here. This is for an out of tree backend im writing. I managed to reduce it to the following C function:
void foo(int *a) // int here is 16bits
{
*a &= 0xFF;
}
This is the code before regalloc:
Live Ins: %R25R24
%vreg0 = COPY %R25R24; DREGS:%vreg0
%vreg2 = COPY %vreg0; PTRREGS:%vreg2 DREGS:%vreg0
%vreg1 = LDWRd %vreg2; mem:LD2%a(tbaa=!“int”) DLDREGS:%vreg1 PTRREGS:%vreg2
%vreg3 = ANDIWRdK %vreg1, 255; DLDREGS:%vreg3,%vreg1
%vreg5 = COPY %vreg0; PTRREGS:%vreg5 DREGS:%vreg0
STWRr %vreg5, %vreg3; mem:ST2%a(tbaa=!“int”) PTRREGS:%vreg5 DLDREGS:%vreg3
RET
From above, the 3rd COPY instruction is redundant since it does exactly the same thing as the second COPY instruction, so the stw (store) instr should take %vreg2 instead of %vreg5. After regalloc we get this code:
Live Ins: %R25R24
%R27R26 = COPY %R25R24
%R19R18 = LDWRd %R27R26; mem:LD2%a(tbaa=!“int”) // <---------- why is R27:R26 killed?
%R19R18 = ANDIWRdK %R19R18, 255
%R27R26 = COPY %R25R24 // <------------------ why is this emitted?
STWRr %R27R26, %R19R18; mem:ST2%a(tbaa=!“int”)
RET
The last copy instruction should be removed as pointed out above, but since R27R26 is killed in the load instruction it has to be emitted. About the insane amount of regclasses there, the load/store and the andi instructions take subsets of regs from the main register class, they cant work with all registers, that’s why STW and LDW needs R27R26 since it belongs to the ptr reg class and not R25R24 where the “a” ptr is. As a test i made the load/store instructions work with the DREGS which is the main class and the problem was solved, but of course this is illegal code 
Thanks